The present invention relates to clocking circuits for digital systems. More specifically, the present invention relates to a clocking circuit using a filter to provide low jitter clock signals.
Clock signals are used for a variety of purpose in digital circuits on both board level systems and integrated circuit (IC) devices, such as transceivers, field programmable gate arrays (FPGAs) and microprocessors. For example, in transceivers, clock signals are used to clock out data bits. Clock signals are typically generated using a phase locked loop (PLL).
FIG. 1 shows a conventional phase locked loop 100 used to generate a PLL output clock signal PLL_O_CLK. Phase locked loop 100 receives a reference clock signal REF_CLK having a frequency F_REF and generates a PLL output clock signal PLL_O_CLK having a frequency F_OUT, where F_OUT is equal to frequency F_REF multiplied by a multiplier, i.e. F_OUT=F_REF*M. Phase locked loop 100 comprises a phase and frequency comparator 110, a charge pump 120, a voltage controlled oscillator (VCO) 140, and a clock divider 150. Clock divider 150 divides PLL output clock signal PLL_O_CLK to generate a feedback clock signal FBK_CLK having a frequency F_FBK equal to frequency F_OUT divided by M.
Phase and frequency comparator 110 compares the phase and frequency of feedback clock FBK_CLK to the phase and frequency of reference clock signal REF_CLK. Specifically, if an active edge of feedback clock signal FBK_CLK leads an active edge of reference clock signal REF_CLK, frequency comparator 110 causes charge pump 120 to decrease the voltage level of VCO control signal VCO_C, which is coupled to voltage controlled oscillator 140, to reduce frequency F_OUT of PLL output clock signal PLL_O_CLK, which is generated by voltage controlled oscillator 140. Conversely, if an active edge of feedback clock signal FBK_CLK lags an active edge of reference clock signal REF_CLK, frequency comparator 110 causes charge pump 120 to increase the voltage level of VCO control signal VCO_C to increase frequency F_OUT of PLL output clock signal PLL_O_CLK. Thus, eventually, the phase and frequency of feedback clock signal FBK_CLK is nearly equal to the phase and frequency of reference clock signal REF_CLK. As explained above, frequency F_FBK of feedback clock signal FBK_CLK is equal to frequency F_OUT of PLL output clock signal PLL_O_CLK divided by M, i.e., F_FBK=F_OUT/M. Thus, frequency F_OUT of PLL output clock signal PLL_O_CLK is equal to frequency F_REF of reference clock signal REF_CLK multiplied by M, i.e., F_OUT=F_REF*M. Generally, PLL output clock signal PLL_O_CLK would be provided to a clock buffer (not shown) and then distributed to the other components of the chip or system.
As explained above, phase locked loop 100 converges on the proper phase and frequency for PLL output clock signal PLL_O_CLK by controlling voltage controlled oscillator 140. In general, phase locked loop 100 can not perfectly align the phase and frequency of feedback clock signal FBK_CLK with the phase and frequency of reference clock signal REF_CLK, due to finite phase locked loop bandwidth. Instead, frequency F_FBK bounces around a very narrow range around frequency F_REF. Consequently, frequency F_OUT of PLL output clock signal PLL_O_CLK bounces around a very narrow range around M times frequency F_REF. The slight changes in frequency F_OUT causes jitter on PLL clock signal PLL_O_CLK. If frequency F_OUT is small, i.e. the clock period is long, the small jitter in PLL output clock signal PLL_O_CLK can typically be ignored. However, if frequency F_OUT of PLL output clock signal PLL_O_CLK is high and the clock period of PLL output clock signal PLL_O_CLK is small, the jitter in PLL output clock signal PLL_O_CLK may be a significant portion of the clock period. Generally, the jitter must be reduced to a small portion of the clock period otherwise serious problems may develop in a high-speed chip or system. Hence, there is a need for a clock generating system, which minimizes jitter in an output clock signal.
Accordingly, a post PLL filter is coupled to the output terminal of a phase locked loop. The post PLL filter reduces the jitter of the PLL output clock signal by increasing the Q (wherein Q is the quality factor) of the phase locked loop. In addition, some embodiments of the present invention also provide amplitude magnification of the PLL output clock signal.
In accordance with one embodiment of the present invention, the post PLL filter is an active band pass filter using complementary input and output signals. The active band pass filter uses the inherent capacitance on the output clock lines rather than requiring additional capacitors. By using the inherent capacitance on the output clock lines, the active band pass filter provides amplitude magnification at the desired clock frequency. The PLL output clock signal is received on the control terminals of two input transistors. A pair of inductors coupled in series between a P output terminal and an N output terminal provides the inductance of the active band pass filter. A pair of cross coupled transistors provide negative Gm and boosts the Q factor of the active band pass filter. A varacter coupled between the P output terminal and the N output terminal can be used to tune the active band pass filter. In a second embodiment of the present invention, the post PLL filter includes multiple band pass filters to further boost the output clock signal.
The present invention will be more fully understood in view of the following description and drawings.